? semiconductor components industries, llc, 2005 march, 2005 ? rev. 9 1 publication order number: mc1489/d mc1489, MC1489A quad line eia-232d receivers the mc1489 monolithic quad line receivers are designed to interface data terminal equipment with data communications equipment in conformance with the specifications of eia standard no. eia?232d. features ? input resistance ? 3.0 k to 7.0 k ? input signal range ? 30 v ? input threshold hysteresis built in ? response control a) logic threshold shifting b) input noise filtering ? pb?free packages are available mdtl logic output interconnecting cable interconnecting cable mdtl logic input line receiver mc1489 figure 1. simplified application line driver mc1488 pdip?14 p suffix case 646 1 14 soic?14 d suffix case 751a 1 14 see general marking information in the device marking section on page 8 of this data sheet. device marking information see detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ordering information 1 1 14 soeiaj?14 m suffix case 965 pin connections input d 13 response control b input a response control a 1 ground input b 2 output c response control c output d v cc 14 response control d output a input c output b 8 9 10 11 12 7 5 3 4 6 http://onsemi.com *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc1489, MC1489A http://onsemi.com 2 figure 2. representative schematic diagram (1/4 of circuit shown) 3.8 k input 1 r f response control 2 1.7 k 5.0 k 10 k 7 gnd 3 output 14 v cc 9.0 k mc1489 MC1489A r f 6.7 k 1.6 k
mc1489, MC1489A http://onsemi.com 3 maximum ratings (t a = + 25 c, unless otherwise noted) rating symbol value unit power supply voltage v cc 10 vdc input voltage range v ir 30 vdc output load current i l 20 ma power dissipation (package limitation, soic?14 and plastic dual in?line package) derate above t a = + 25 c p d 1/ ja 1000 6.7 mw mw/ c operating ambient temperature range t a 0 to + 75 c storage temperature range t stg ? 65 to + 175 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. electrical characteristics (response control pin is open.) (v cc = + 5.0 vdc 10%, t a = 0 to + 75 c, unless otherwise noted) characteristics symbol min typ max unit positive input current (v ih = + 25 vdc) (v ih = + 3.0 vdc) i ih 3.6 0.43 ? ? 8.3 ? ma negative input current (v ih = ? 25 vdc) (v ih = ? 3.0 vdc) i il ? 3.6 ? 0.43 ? ? ? 8.3 ? ma input turn?on threshold voltage (t a = + 25 c, v ol 0.45 v) mc1489 MC1489A v ih 1.0 1.75 ? 1.95 1.5 2.25 vdc input turn?off threshold voltage (t a = + 25 c, v oh 2.5 v, i l = ? 0.5 ma) mc1489 MC1489A v il 0.75 0.75 ? 0.8 1.25 1.25 vdc output voltage high (v ih = 0.75 v, i l = ? 0.5 ma) (input open circuit, i l = ? 0.5 ma) v oh 2.5 2.5 4.0 4.0 5.0 5.0 vdc output voltage low (v il = 3.0 v, i l = 10 ma) v ol ? 0.2 0.45 vdc output short?circuit current i os ? ? 3.0 ? 4.0 ma power supply current (all gates aon,o i out = 0 ma, v ih = + 5.0 vdc) i cc ? 16 26 ma power consumption (v ih = + 5.0 vdc) p c ? 80 130 mw switching characteristics (v cc = 5.0 vdc 1%, t a = + 25 c, see figure 3.) propagation delay time (r l = 3.9 k ) t plh ? 25 85 ns rise time (r l = 3.9 k ) t tlh ? 120 175 ns propagation delay time (r l = 390 k ) t phl ? 25 50 ns fall time (r l = 390 k ) t thl ? 10 20 ns
mc1489, MC1489A http://onsemi.com 4 v in v r all diodes 1n3064 or equivalent e o r t tlh and t thl measured 10% - 90% figure 3. switching response c 1/4 MC1489A r l 5.0 vdc 50% 50% 3.0 v e in t thl c l = 15 pf = total parasitic capacitance which includes probe and wiring capacitances 1.5 v 1.5 v t tlh t plh response node v o e in c l c, capacitor is for noise filtering. r, resistor is for threshold shifting. e o figure 4. response control node test circuits
mc1489, MC1489A http://onsemi.com 5 typical characteristics (v cc = 5.0 vdc, t a = +25 c, unless otherwise noted) v in , input voltage (v) 10 0 -10 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 8.0 10 -25 -20 -15 -10 -5.0 5.0 15 25 20 i , input current (ma) l figure 5. input current i i v i r t r t 5.0 k v th 5.0 v r t 13 k v th 5.0 v 6.0 5.0 4.0 3.0 2.0 1.0 0 3.0 2.0 1.0 0 -2.0 -1.0 -3.0 v i , input voltage (v) v ilh v , output voltage (vdc) o v ihl e o v th r t v i r t 11 k v th -5.0 v figure 6. mc1489 input threshold voltage adjustment r t v i , input voltage (v) 3.0 4.0 5.0 6.0 1.0 2.0 0 4.0 -2.0 -1.0 -3.0 2.0 1.0 0 3.0 v , output voltage (vdc) o r t 5.0 k v th 5.0 v r t 11 k v th -5.0 v figure 7. MC1489A input threshold voltage adjustment e o v th r t v in v ihl v ilh mc1489 v ih mc1489 v il t, temperature ( c) +120 +60 0 -60 0 0.2 0.4 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 2.2 2.4 v , input threshold voltage (vdc) ih MC1489A v il MC1489A v ih figure 8. input threshold voltage versus temperature v ih MC1489A v ih mc1489 v il mc1489 v il MC1489A v cc , power supply voltage (v) 4.0 5.0 6.0 0 3.0 2.0 1.0 input threshold voltage (vdc) figure 9. input threshold versus power supply voltage
mc1489, MC1489A http://onsemi.com 6 applications information general information the electronic industries association (eia) has released the eia?232d specification detailing the requirements for the interface between data processing equipment and data communications equipment. this standard specifies not only the number and type of interface leads, but also the voltage levels to be used. the mc1488 quad driver and its companion circuit, the mc1489 quad receiver, provide a complete interface system between dtl or ttl logic levels and the eia?232d defined levels. the eia?232d requirements as applied to receivers are discussed herein. the required input impedance is defined as between 3000 and 7000 for input voltages between 3.0 and 25 v in magnitude; and any voltage on the receiver input in an open circuit condition must be less than 2.0 v in magnitude. the mc1489 circuits meet these requirements with a maximum open circuit voltage of one v be . the receiver shall detect a voltage between ? 3.0 and ?25 v as a logic a1o and inputs between 3.0 and 25 v as a logic a0.o on some interchange leads, an open circuit of power aoffo condition (300 or more to ground) shall be decoded as an aoffo condition or logic a1.o for this reason, the input hysteresis thresholds of the mc1489 circuits are all above ground. thus an open or grounded input will cause the same output as a negative or logic a1o input. device characteristics the mc1489 interface receivers have internal feedback from the second stage to the input stage providing input hysteresis for noise rejection. the mc1489 input has typical turn?on voltage of 1.25 v and turn?off of 1.0 v for a typical hysteresis of 250 mv. the MC1489A has typical turn?on of 1.95 v and turn?off of 0.8 v for typically 1.15 v of hysteresis. each receiver section has an external response control node in addition to the input and output pins, thereby allowing the designer to vary the input threshold voltage levels. a resistor can be connected between this node and an external power supply. figures 4, 6 and 7 illustrate the input threshold voltage shift possible through this technique. this response node can also be used for the filtering of high frequency, high energy noise pulses. figures 10 and 11 show typical noise pulse rejection for external capacitors of various sizes. these two operations on the response node can be combined or used individually for many combinations of interfacing applications. the mc1489 circuits are particularly useful for interfacing between mos circuits and mdtl/mttl logic systems. in this application, the input threshold voltages are adjusted (with the appropriate supply and resistor values) to fall in the center of the mos voltage logic levels (see figure 12). the response node may also be used as the receiver input as long as the designer realizes that he may not drive this node with a low impedance source to a voltage greater than one diode above ground or less than one diode below ground. this feature is demonstrated in figure 13 where two receivers are slaved to the same line that must still meet the eia?232d impedance requirement. pw, input pulse width (ns) 500 pf mc1489 6 5 4 3 2 1 10,000 1000 100 10 300 pf 100 pf 10 pf e , amplitude (v) in figure 10. typical turn on threshold versus capacitance from response control pin to gnd MC1489A pw, input pulse width (ns) 12 pf 500 pf 100 pf 300 pf 6 5 4 3 2 1 10,000 1000 100 10 e , amplitude (v) in figure 11. typical turn on threshold versus capacitance from response control pin to gnd
mc1489, MC1489A http://onsemi.com 7 figure 12. typical translator application ? mos to dtl or ttl response-control pin 1/2 mc1489 response-control pin input v cc 8.0 k v cc input output output +5.0 vdc +5.0 vdc dtl or ttl r +5.0 vdc -v dd mc1489 -v gg mos logic figure 13. typical paralleling of two mc1489, a receivers to meet eia?232d 8.0 k
mc1489, MC1489A http://onsemi.com 8 ordering information device package operating temperature range shipping 2 mc1489d soic?14 55 units/rail mc1489dg soic?14 (pb?free) 55 units/rail mc1489dr2 soic?14 2500 tape & reel mc1489dr2g soic?14 (pb?free) 2500 tape & reel MC1489Ad soic?14 55 units/rail MC1489Adg soic?14 (pb?free) 55 units/rail MC1489Adr2 soic?14 2500 tape & reel MC1489Adr2g soic?14 (pb?free) t a = 0 to +75 c 2500 tape & reel mc1489p pdip?14 25 units/rail mc1489pg pdip?14 (pb?free) 25 units/rail MC1489Ap pdip?14 25 units/rail MC1489Apg pdip?14 (pb?free) 25 units/rail mc1489m 50 units/rail mc1489mel soeiaj 14 2000 tape & reel MC1489Am soeiaj?14 50 units/rail MC1489Amel 2000 tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week pdip?14 p suffix case 646 soic?14 d suffix case 751a 1 14 MC1489Ap awlyyww 1 14 mc1489p awlyyww MC1489A alyw soeiaj?14 m suffix case 965 mc1489 alyw MC1489Ad awlyww 1 14 mc1489d awlyww 1 14
mc1489, MC1489A http://onsemi.com 9 package dimensions soic?14 d suffix case 751a?03 issue g notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ?a? ?b? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ?t? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 pdip?14 p suffix case 646?06 issue m 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 18.80 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m --- 10 --- 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n ?t? 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87
mc1489, MC1489A http://onsemi.com 10 package dimensions soeiaj?14 m suffix case 965?01 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mc3423/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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